Embodiments of the present invention relate to an array substrate and a manufacturing method thereof.
Currently, Thin Film Transistor Liquid Crystal Displays (TFT-LCDs) have a variety of electric field display modes, such as ADS (Advanced Super Dimension Switch), In-Plane Switching (IPS), (Vertical Alignment) VA, etc, and in different display modes, they have different design structures. Thus, they not only differ remarkably in terms of quality of products, but also have a large difference in fabrication process of an array substrate as well.
FIG. 1 shows the structure of an array substrate of an IPS display mode, which comprises a base substrate 11, a pixel electrode 12 and a common electrode 13. Its pixel electrode 12 and common electrode 13 are arranged alternately on the same plane, so as to form electric fields in the directions of arrows in FIG. 1. Based on the structure shown in FIG. 1, a four-patterning process (i.e. 4 masks) is used to fabricate the array substrate of the IPS display mode, specifically, it comprises: patterning of a gate line and a gate electrode, patterning of an active layer, a data line and source and drain electrodes, patterning of a via hole, and patterning of a pixel electrode and a common electrode. That is, in the array substrate of IPS display mode, the pixel electrode and the common electrode are formed in the same patterning process.
FIG. 2 shows the structure of an array substrate of an ADS display mode, which comprises a base substrate 21, a pixel electrode 22 and a common electrode 23, and its pixel electrode 22 and common electrode 23 are arranged in an upper layer and a bottom layer, respectively. As shown in FIG. 2, the pixel electrode 22 is located in the upper layer and composed of a transparent electrode pattern with a slit structure, an insulating layer is provided between the pixel electrode 22 and the common electrode 23, and the common electrode 23 is located in the lower layer and disposed at least in positions corresponding to slits in the pixel electrode 22, so as to form electric fields in the directions of arrows in FIG. 2. Based on the structure shown in FIG. 2, a (1+4)-patterning process (i.e. (1+4) masks) is used to fabricate the array substrate of the ADS display mode, and as compared to the four-patterning process for the array substrate of the IPS display mode, it is necessary for this manufacturing method to form the pixel electrode and the common electrode, respectively. Thus, the (1+4)-patterning process used for the array substrate in the ADS display mode has one more patterning step than the four-patterning process used for the array substrate in the IPS display mode.
As can be seen from FIG. 1 and FIG. 2, when compared with the array substrate of the IPS display mode, the array substrate of the ADS display mode has the following features. The controllable area of an electric field formed by a pixel electrode and a common electrode of the array substrate of the ADS display mode is wider, and thus it is better than that of the IPS display mode in terms of transmittance, luminance, contrast, etc. However, there is a relatively large overlapping zone between the pixel electrode and the common electrode in the array substrate of the ADS display mode, and a larger storage capacitance may be formed, causing Greenish (greenish picture), line image sticking and other disadvantageous quality defect, which will be more and more obvious as the size of a panel becomes larger. Further, the (1+4)-patterning process used for the array substrate in the ADS display mode is more cockamamie than the four-patterning process used for the array substrate in the IPS display mode, and the production cost will be a little higher as well.
In summary, the array substrate of the ADS display mode and the array substrate of the IPS display mode each have their own advantages and disadvantages, and therefore, to produce a new array substrate of an edge-electric-field display mode capable of combining the merits of the two has become an important research subject.